1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, in particular, to a trench capacitor in a semiconductor memory device such as a DRAM and a method for manufacturing the same.
2. Description of the Related Art
In a manufacturing process and structure of a trench capacitor in the conventional technique, a polysilicon of a storage node section is limited to one either wholly formed of an As (Arsenic)-doped polysilicon or partly using a non-doped polysilicon.
That is, as shown in FIG. 17, a trench 52 is provided in a P-type silicon substrate 51 and, in the trench 52, an As-doped polysilicon layer 55 is buried through an insulating film 53 and collar insulating film 54, and an As-doped buried strap layer 56 is formed on the As-doped polysilicon layer 55.
Further, an isolation region 57 is provided by an STI technique on the surface portion of the trench capacitor. Adjacent to the trench capacitor a gate electrode 62 is provided on the surface of a substrate through a gate insulating film 61. A sidewall insulating film 63 is formed on the side surface of the gate electrode 62. Further, a source or drain region 64 is provided and, through the diffusion of As from the As-doped buried strap layer 56, a strap region 65 is so formed as to overlap the source or drain region 64.
Since, in this case, the diffusion coefficient is small, the BS (Buried Strap) diffusion length is shorter to provide an advantage of, for example, suppressing a short channel effect of a cell transistor. However, since the junction edge of the BS diffusion region is As, the junction leakage is increased to degrade the data retaining characteristic.
In order to eliminate such a disadvantage, in the prior art, such countermeasures are taken that, after the wet treatment of the collar oxide film, phosphorus (P) ions are implanted into a silicon sidewall or that after etching back the As-doped polysilicon layer 55, P ions are implanted from a vertical direction to cover a junction 58 below the BS diffusion region with P.
However the above-mentioned methods are breaking down due to the fine device structure of the design rule. Further, in the method of directly implanting P into the BS sidewall, P is implanted to a given depth from the side surface of the substrate at the ion implantation. Therefore, P will be more deeply diffused by a later thermal process, thereby degrading the characteristics of transistors.
In the case where after the As-doped polysilicon layer is etched back, P is implanted vertically from a direction of an upper portion, an effect of P contamination will be exerted, due to its lateral diffusion at the ion implantation, not only on significant bit cells but also on adjacent bit cells, so that the characteristics of the transistors will be similarly degraded.